1. Field of the Invention
The present invention relates to a phase shift mask and fabricating method thereof, by which a critical dimension of a semiconductor pattern can be accurately formed in a manner that compensates for a boundary step difference between an active area and an insulating layer.
2. Discussion of the Related Art
Generally, a mask pattern forming technique is closely related to a precision of a real pattern formed on a semiconductor substrate. Specifically, if a degree of semiconductor pattern integration is very high, a remaining space for inserting an OPC (optical proximity correction) pattern therein is insufficient, and consequently a line width bridge between patterns unexpectedly occurs regardless of lithography exposure intention, and various device characteristic are degraded.
In semiconductor photolithography, a precise design of a photomask enables a quantity of light transmitted via the photomask to be appropriately adjusted. For the precise design of the photomask, OPC, phase shift masking, and the like has been proposed as well as various methods for minimizing the light distortion attributed to a shape of the pattern drawn on a mask.
Lately, a chemically amplified resist having excellent sensitivity to far infrared ray wavelength (248˜194 nm) has been developed to substantially enhance resolution. And, the resolution enhancement is attributed to a technique of forming a supplementary (dummy) pattern separated from the real pattern to control an optical proximity effect.
FIG. 1 is a layout of a mask according to a related art, in which a logic device part is shown.
Referring to FIG. 1, a logic device part of a mask consists of a square type active area shield pattern 2 on a transparent substrate 1 and a pair of bar type gate shield patterns 3 and 4 on the active area shield pattern 2 to be overlapped with the active area shield pattern 2. Each end of the gate shield patterns 3 and 4 protrudes outside from a rim of the active area shield pattern 2 to a prescribed length L.
FIG. 2 is a layout of a semiconductor device formed using the mask in FIG. 1, and FIG. 3 is a cross-sectional diagram along a cutting line A-A in FIG. 2.
Referring to FIG. 2, an insulating layer 11 and an active layer 12 are formed on a substrate 10 to correspond to the transparent substrate 1 and the active area shield pattern 2 of the mask, respectively. Namely, the active layer 12 is formed on the substrate 10 to have the same shape of the active area shield pattern 2 of the mask and the insulating layer 11 is formed to enclose the active layer 12 to correspond to the transparent substrate 1 of the mask.
Gate patterns 13 and 14 are formed on the insulating layer 11 and the active layer 12 to correspond to the gate shield patterns 3 and 4 of the mask. Specifically, front ends of the gate patterns 13 and 14 protrude from a boundary of the active layer 12 to a prescribed length L′ like the shield patterns 3 and 4.
Compared to the protruding front end length L of each of the gate shield patterns 3 and 4 of the mask, the protruding end length L′ of each of the gate patterns 13 and 14 is shortened due to the optical proximity effect and the boundary step difference between the insulating layer 11 and the active layer 12.
However, if the front end length of the gate pattern 13 or 14 is shortened, it is not possible to secure a process margin of the active layer 12, and a gate threshold voltage is raised.